An improved systolic architecture for 2-D digital filters

An improved systolic architecture for two-dimensional infinite-impulse-response (IIR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work 121, [3] are made. When compared with the architecture in [2], a substantial reduction in the number of delay elements is observed. This reduction is of the order of 10’ for a 2-D IIR filter and equals N + 1 for an Nth order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speed-up factor is the maximum achievable and is independent of the filter order. Comparison with [3] shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N + 1 delay elements has been achieved for the FIR filter. An error analysis for the new architecture is made, while error expressions for the architectures in [2], [3] are also presented.